Espressif Systems /ESP32-P4 /HP_SYS_CLKRST /PERI_CLK_CTRL20

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PERI_CLK_CTRL20

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0REG_MCPWM0_CLK_SRC_SEL 0 (REG_MCPWM0_CLK_EN)REG_MCPWM0_CLK_EN 0REG_MCPWM0_CLK_DIV_NUM 0REG_MCPWM1_CLK_SRC_SEL 0 (REG_MCPWM1_CLK_EN)REG_MCPWM1_CLK_EN 0REG_MCPWM1_CLK_DIV_NUM 0REG_TIMERGRP0_T0_SRC_SEL 0 (REG_TIMERGRP0_T0_CLK_EN)REG_TIMERGRP0_T0_CLK_EN 0REG_TIMERGRP0_T1_SRC_SEL 0 (REG_TIMERGRP0_T1_CLK_EN)REG_TIMERGRP0_T1_CLK_EN 0REG_TIMERGRP0_WDT_SRC_SEL 0 (REG_TIMERGRP0_WDT_CLK_EN)REG_TIMERGRP0_WDT_CLK_EN 0 (REG_TIMERGRP0_TGRT_CLK_EN)REG_TIMERGRP0_TGRT_CLK_EN

Description

Reserved

Fields

REG_MCPWM0_CLK_SRC_SEL

Reserved

REG_MCPWM0_CLK_EN

Reserved

REG_MCPWM0_CLK_DIV_NUM

Reserved

REG_MCPWM1_CLK_SRC_SEL

Reserved

REG_MCPWM1_CLK_EN

Reserved

REG_MCPWM1_CLK_DIV_NUM

Reserved

REG_TIMERGRP0_T0_SRC_SEL

Reserved

REG_TIMERGRP0_T0_CLK_EN

Reserved

REG_TIMERGRP0_T1_SRC_SEL

Reserved

REG_TIMERGRP0_T1_CLK_EN

Reserved

REG_TIMERGRP0_WDT_SRC_SEL

Reserved

REG_TIMERGRP0_WDT_CLK_EN

Reserved

REG_TIMERGRP0_TGRT_CLK_EN

Reserved

Links

() ()